UGC Approved Journal no 63975(19)

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Published in:

Volume 7 Issue 12
December-2020
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2012029


Registration ID:
304119

Page Number

198-205

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Title

Experimental Validation of Asymmetric Multilevel Inverter with Single Phase Transformer

Authors

Abstract

In this paper, the hardware implementation of the modified asymmetric multilevel inverter with a single-phase transformer is presented. The multilevel inverter has been enforced for reducing the bulkiness of the LC filter size as well as the cost of the system. Since the inverter is fed by a three asymmetric DC source, asymmetry is enforced providing multiple redundant switching patterns to synthesize an output signal of 13 levels. Optimum switching patterns are developed for the proposed ratio which allows reducing typical switches count as well as harmonics to 5% under IEEE standards. .The concept of reduced device count ensures the size of hardware as well as the cost and complexity of the hardware. The main drawback of multilevel inverters is, requires a high number of switching devices leads to complex control. The proposed topology utilizes three asymmetrical dc voltage sources alongside, ten power semiconductor switches to accomplish thirteen levels at the output. Compared to the conventional topologies, the proposed inverter has less number of switches as well as fewer harmonics content. Transformer based multilevel inverter is expected to give isolation protection. The proposed cascaded H-bridge topology has high efficiency as well as balanced power distribution quality. The simple PWM technique is utilized for the generation of pulses to the multilevel inverter switches which increase the simplicity of the control. Further, extensive hardware validation shows the effectiveness of the system.

Key Words

Multi Level Inverter, THD, CHB Topology, Asymmetric Transformer.

Cite This Article

"Experimental Validation of Asymmetric Multilevel Inverter with Single Phase Transformer", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 12, page no.198-205, December-2020, Available :http://www.jetir.org/papers/JETIR2012029.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Experimental Validation of Asymmetric Multilevel Inverter with Single Phase Transformer", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 12, page no. pp198-205, December-2020, Available at : http://www.jetir.org/papers/JETIR2012029.pdf

Publication Details

Published Paper ID: JETIR2012029
Registration ID: 304119
Published In: Volume 7 | Issue 12 | Year December-2020
DOI (Digital Object Identifier): http://doi.one/10.1729/Journal.25127
Page No: 198-205
Country: CHENNAI, Tamil Nadu, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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